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Binary logic
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#	Item
221	Logic Synthesis for Regular Layout using Satisfiability Marek Perkowski and Alan Mishchenko Department of Electrical and Computer Engineering Portland State University Portland, OR 97207, USA [mperkows, alanmi]@ece.pdx.e Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2002-05-01 01:40:28 Theoretical computer science Electronic design automation Diagrams Formal methods Lattice theory Binary decision diagram Boolean satisfiability problem Logic synthesis Lattice Abstract algebra Mathematics Boolean algebra
222	Optimization of Multi-Valued Multi-Level Networks M. Gao, J-H. Jiang, Y. Jiang, Y. Li, A. Mishchenko, S. Sinha, T. Villa, and R. Brayton Electrical Engineering and Computer Sciences Dept. University of California, Ber Add to Reading List Source URL: www.bvsrc.org Language: English* - Date: 2004-06-17 16:08:02 Diagrams Model checking Many-valued logic Flip-flop Electronics Mathematics Mathematical logic Electronic engineering Binary decision diagram Boolean algebra
223	ATTITUDES AND COGNITIVE ORGANIZATION Fritz Heider[removed]First published in The Journal of Psychology, 21, [removed]Attitudes towards persons and causal unit formations influence each other. An attitude towards an event Add to Reading List Source URL: snap.stanford.edu Language: English - Date: 2013-09-11 13:28:24 Mathematical logic FO Binary relation Existential quantification Science Logic Mathematics Finitary relation
224	LUTMIN: FPGA Logic Synthesis with MUX-Based and Cascade Realizations Tsutomu Sasao 1 and Alan Mishchenko[removed]Dept. of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka[removed], Japan Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2009-07-09 02:20:06 Boolean algebra Diagrams Field-programmable gate array Binary decision diagram Lookup table Xilinx Multiplexer Artificial neuron Function Computing Mathematics Electronic engineering
225	Previous chapter 60 compiling bsp trees Add to Reading List Source URL: downloads.gamedev.net Language: English - Date: 2011-08-09 01:03:18 3D computer graphics Binary space partitioning Curve Tree Line BSP ALGOL 68 Mathematical logic Mathematics Geometry
226	An Introduction to Zero-Suppressed Binary Decision Diagrams Alan Mishchenko Department of Electrical and Computer Engineering Portland State University, Portland, OR 97207, USA [removed]; http://www.ee.pdx.edu/~a Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2001-09-30 22:57:32 Boolean algebra Algebraic logic Diagrams Computability theory Binary decision diagram Model checking Indicator function Recursion Function Mathematics Mathematical logic Mathematical analysis
227	FRAIGs: A Unifying Representation for Logic Synthesis and Verification Alan Mishchenko, Satrajit Chatterjee, Roland Jiang, Robert Brayton Department of EECS, University of California, Berkeley {alanmi, satrajit, jiejiang Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-04-01 15:19:32 Boolean algebra Diagrams Digital electronics And-inverter graph Binary decision diagram Logic optimization Model checking Boolean function Logic synthesis Electronic engineering Electronic design automation Formal methods
228	Microsoft Word - iwls07-final.doc Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2007-05-01 11:44:52 Boolean algebra Electronic design automation Formal methods Logic in computer science NP-complete problems Boolean satisfiability problem Binary decision diagram Functional dependency Conjunctive normal form Theoretical computer science Mathematics Mathematical logic
229	Characteristic Formulae for Fixed-Point Semantics: A General Framework∗ Luca Aceto Anna Ingolfsdottir Add to Reading List Source URL: www.ru.is Language: English - Date: 2009-06-14 06:08:27 Metalogic Binary operations Model theory Propositional calculus Bisimulation Logical equivalence Interpretation If and only if Entailment Logic Mathematics Mathematical logic
230	VLSI DESIGN 2001, Vol. 12, No. 3, pp[removed]Reprints available directly from the publisher Photocopying permitted by license only (C[removed]OPA (Overseas Publishers Association) N.V. Add to Reading List Source URL: downloads.hindawi.com Language: English - Date: 2014-05-08 05:38:12 Electronics Electrical circuits Digital circuits Digital signal processing Adder Binary logic Clock signal Multiply–accumulate operation Propagation delay Electronic engineering Computer arithmetic Electrical engineering

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